As background for the method which will be described, simulations have been used in the creation of silicon devices, including thin film devices made by a process known as silicon-on-insulator (also called SOI) to make SOI devices. SOI device performance depends on the current voltage on the floating body of the device (including circuits). This body voltage depends, in turn, on the switching history of the device (or circuit). Simulations used in the creation of silicon devices (including circuits) include conventional delay measurement processes, but until the development of the techniques referenced in the related applications, there was no known simulation techniques which have a way to account for the effect of current body voltage. Prior methods of accounting for the history effect of the current body voltage required either simulating the exact history in question, or trying to bound the problem. Neither method is applicable to delay rules. Neither method allows correction for ordering of simulations within one run. Theoretically, accounting for the effect of current body voltage would be possible by simulating the entire switching history, but this is not practical and so conventional delay estimation processes do not have a way to account for this effect at all. Furthermore, as the usual procedure was to measure delays for several different loads in one simulation run, the use of a simulation history would not be acceptable. This dependence on the history of the simulation will give different, unpredictable results depending on the order of the simulation runs.
We have concluded that there is needed a way to simulate the effect in a way that can be used in a system used for simulating electrical delay such as those illustrated by Mitsubishi Denki K. K.'s U.S. Pat. No. 5,396,615 and Hitachi Micro Systems Inc.'s U.S. Pat. No. 5,384,720, as general examples of electrical simulation and design systems and yet to date this has not been achieved by others.
We would note that there are numerous publications and patents, which could be used to illustrate what others do with SOI devices, and what simulation techniques have been used. Among those are those referenced in this patent disclosure, and prior applications, including an unpublished report at International Business Machines Corporation in January, 1993 Messrs. Dubois,(E.); Shahidi, (G. G.) and Sun,(J. Y. C.) printed their "Analysis of the Speed Performance of Thin Film CMOS/SOI Ring Oscillators" in which they noted, after analyzing the performance advantage of thin-film SOI/CMOS ring oscillators over their bulk silicon counterparts using compact analytic modeling for circuit simulation, that most of the speed improvement of SOI over bulk at the time could be explained in terms of reduced threshold voltage, body doping factor and junction capacitance's. Their tabulated model based on DC current measurements of individual devices was also utilized to achieve higher accuracy. A residual discrepancy between simulated and measured propagation delays was found in both approaches. A comparison of the integrated currents and stored charges in the ring oscillators identified the source of this discrepancy in the underestimation of the charging/discharging currents. These researchers determined that transient enhancement of the current was not the source of this discrepancy by an analysis of the supply voltage dependence of the propagation delay. The sensitivity of the DC current characteristics of SOI devices to the ground rules was discussed and found by them to explain systematically poor predictions of the delay per stage by means of circuit simulation. This report was internal to IBM but it shows no way to simulate the effect of current body voltage in SOI device design, and illustrates the dismay of researches as to the poor prediction of delay by circuit simulation in this area.
We concluded that there was needed a way to simulate the effect of current body voltage in SOI circuit device design is needed out yet to date this has not been achieved by others. In efforts at IBM described in the prior applications, partially depleted SOI devices maintain a stored charge in the body of the device. This charge gives rise to the "body voltage". The body voltage, in turn, can influence the threshold voltage (VT) of the device and hence the performance of the circuit.
In the past, with bulk silicon devices, this effect was unimportant. The first referenced related application, U.S. Ser. No. 08/938,676, Filed Sep. 26, 1997, now U.S. Pat. No. 6,023,577, Issued Feb. 8, 2000, described a method where the body voltage can be set randomly, or be set to track process variations. The actual measured body voltage is not completely random. The method shown in the other related disclosures shows methods for trying to get a more accurate representation of the effect of the body voltage.
It is desirable to improve upon these prior breakthroughs, and we will describe a more specialized method to get an estimate of the body voltage. While the method is not as general as in the parent application, it is more accurate where it can be used.